The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having thermally conductive vias to help dissipate heat in multi-dimensional chip packages.
Multi-layer electronic components are typically joined together by soldering pads on a surface of one of the electronic components to corresponding pads on the surface of the other component. Broadly stated, one or more integrated circuit (IC) chips (i.e., dies) are typically connected to an organic carrier through an interposer. The organic carrier may be electrically connected to a single or multi-layer substrate, such as a printed circuit board (PCB). Pads on the IC chips may be electrically and mechanically connected to corresponding pads on the interposer by a plurality of plurality of small-pitch electrical connections (i.e., micro-solder connections). The interposer may then be electrically and mechanically connected to the organic carrier by larger pitch solder connections.
Therefore, the pitch of the solder connections on the top side of the glass interposer (joined to the IC chip) is typically smaller than the pitch of the solder connections on the bottom side of the glass interposer (joined to the organic carrier). Multi-dimensional packages with interposers that use through silicon vias (TSVs) as an electrical pathway from the IC chips to the organic carrier are typically regarded as 2.5D packages.